The present invention relates generally to computer logic and control circuit schemes, and more particularly to a logic control redundancy scheme for use on a single semiconductor chip.
Defects inherent in semiconductor wafers and defects added during fabrication substantially limit the size and manufacturing yield for a given semiconductor chip product. In order to improve manufacturing yield in the presence of such chip defects, various redundancy schemes have been utilized in the art. These redundancy schemes are configured to substitute "good" circuits on the chip in place of defect-ridden circuits when configuring a given logic or control finction on the chip. Such redundancy schemes are especially useful for reconfiguring random logic chips which could not otherwise be economically manufactured in large ship sizes with the necessary manufacturing yield.
However, there still remain a variety of defects which can "kill" an entire chip even when redundancy is used. For example, shorts in external nets can operate to short-out all circuits connected to that defective external net. (In this context, and external net is intended to refer to the signal line or lines that runs from one circuit group to another circuit group in the chip.) Moreover, some schemes permit the propagation of faulty signals, even after the faulty circuit has been removed from the main signal logic path.
Additionally, many redundancy schemes have a severe power consumption problem, as well as a substantial circuit overhead. For example, a number of redundancy schemes use complex voter control circuits to determine which circuits are functional. Such circuits not only require many circuit elements for their implementation, but also add substantial delay to the overall circuit operation.
The invention as claimed is intended to remedy the above-described problems of the prior art.
One advantage offered by the present invention is that external net shorts can no longer "kill" the entire chip. Additionally, the present invention prevents faulty signals from a defective circuit from propagating, and ensures that, in most cases, there are two "good" signals present on parallel redundant channels. Moreover, the foregoing advantages are achieved with a significant reduction of chip power consumption, circuit complexity and delay relative to normal redundancy schemes.